![]() I don't know what is wrong because my set is 4 and my capture is 13 and it is a up counter. The DCDHEX display shows random numbers while it's on, and it should show 4-12. Unlike the Master-Slave design, which needs a complete pulse, you can also build an edge-triggered design that triggers from a rising edge ↑ or a falling edge ↓. 04-15-2016 07:50 PM Options I'm trying to create a 4-12 asynchronous up JK Flip-flop counter for a project. That’s why this configuration is called pulse-triggered JK Flip-Flop. So this circuit requires a complete pulse (0→1 →0) in order to change the output. Once the clock signal produces a falling edge ↓, a change from 1 to 0 (1→0), it triggers the slave section, causing the Q output to reflect the master’s output value. These signals are connected to the slave section, but this doesn’t trigger on the rising edge because the clock has been inverted. As a result, the value of the outputs in this section changes. As soon as the clock makes a rising edge ↑, which is a change from 0 to 1 (0→1), it triggers the master section. ![]()
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